The present invention concerns multilayer ceramic capacitors having multiple capacitor plates which are terminated at a common face and more particularly, relates to improvements to multilayer capacitors resulting in greater flexibility in use and ease in manufacturing.
The continuing objective of data processing equipment designers is to produce equipment having increased operating speed, reduced physical size and lower manufacturing cost.
Advances in integrated circuit technology have gone a long way to satisfy this objective. One particular area of concentration is the capacitor. In an effort to get ever greater switching speed, circuit designers have gone to a decoupling capacitor which provides a low impedance path across the power supply to power the semiconductor chips without coupling noise into the signal wiring. The noise, if coupled, could cause errors in the computer functions. Such decoupling capacitors are discrete, i.e. separate from the chips. However, to retain the advantages of integrated form, the circuit designers have sought discrete capacitors of small size, maximum capacitance, high speed (rapid responding), low inductance, low resistance and reasonable cost.
The capacitor frequently suggested for use today in this particular application is the multilayer ceramic capacitor. This capacitor consists of a series of parallel plates which are laminated together. Each of these plates consists of a sheet of ceramic dielectric material and a metallic plate. For convenience, the dielectric material may be simply metallized to form each parallel plate. Each of the metallic plates has one or more laterally spaced tabs which may or may not terminate at a common side so as to form longitudinal rows of tabs. Each row of tabs is connected one to the other by a shorting bar or electrode. Final connection of the capacitor to the chips may be conveniently accomplished by surface mounting techniques or, more preferably, by flip-chip mounting the capacitor on a multilayer ceramic substrate with the use of solder balls as disclosed, for example, in Bajorek et al. U.S. Pat. No. 4,349,862, the disclosure of which is incorporated by reference herein. Instead of solder balls, an array of solder bars may be used as disclosed in Chance et al. U.S. Pat. No. 4,430,690, the disclosure of which is incorporated by reference herein.
Other types of multilayer ceramic capacitors are disclosed, for example, in Swart et al. U.S. Pat. No. 3,398,326 and Sakamoto U.S. Pat. No. 4,590,537, the disclosures of which are incorporated by reference herein. In each of these references, the shorting bar or electrode connects all the tabs in each row.
A common characteristic of these multilayer capacitors is that each plate type is assigned to only one voltage and each row of tabs is also assigned to only one voltage. For example, in the IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 1984 (pp. 6595-6597), it is desired to decouple among four different voltages. Each plate type is assigned to only one voltage and each row of tabs is assigned to only one voltage. More importantly, it is necessary to have eleven laterally spaced tabs to accomplish this result. IBM Technical Disclosure Bulletin, Vol. 26, No. 9, February 1984 (p. 4489) and IBM Technical Disclosure Bulletin, Vol. 26, No. 10B, March 1984 (p. 5325) also illustrate the lateral congestion encountered in these types of capacitors. These last two references also illustrate that the tabs may emerge at two common sides of the capacitor, one side being for connection to the substrate with the other side being used for testing or other purposes. All three of these Technical Disclosure Bulletin references are incorporated by reference herein.
Recognizing the problems inherent in properly aligning the tabs and shorting bars which are only a few thousandths of an inch in width, Locke U.S. Pat. No. 4,419,714, the disclosure of which is incorporated by reference herein, proposed a new method of manufacturing the capacitor to correct for misalignment of the tabs and shorting bars. This method essentially consists of putting in grooves in the face of the capacitor to thereby align the tabs or at least eliminate that portion of each tab which is out of alignment.
While the Locke reference provides a way to lessen the problem of lateral congestion, it teaches nothing about eliminating the problem itself. And further, the teaching of Locke is that one plate type may only be assigned to one voltage and each row of tabs may only be assigned to one voltage.
It would be desirable to eliminate the problem of lateral congestion so that solutions such as that proposed in the Locke reference do not need to come into play.
Accordingly, it is an object of the invention to have a capacitor which does not suffer from lateral congestion of the tabs.
It is another object of the invention to have a capacitor which allows for a plurality of assigned voltages so that each row of tabs may be assigned to more than one voltage.
It is still another object of the invention to have a capacitor which is high in speed, reasonable in cost and small in size.
It is yet another object of the invention to have a capacitor which is low in inductance, low in resistance and maximized for capacitance.
These and other objects of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.